The subject matter of the present application relates to multi-layer wiring elements and their fabrication, such as used in the packaging of, or in the connection to micro-electronic elements, particularly semiconductor integrated circuits.
The packaging of microelectronic elements, e.g., semiconductor integrated circuits continually poses new challenges. Processor chips pose particular challenges, due to the large area over which they typically extend, the great number of external contacts which typically are present as pinout at the external signal interface of the chip, and large fluctuations in temperature to which they are subject, because of high operating temperatures of processor chips. Moreover, the pitch and the size of the contacts of the chip are each becoming smaller as the number of external contacts of the chip increases.
Surface mount technology including flip-chip interconnect technology, has been frequently used to interconnect such chips. Flip-chip interconnects can be formed quickly and reliably by holding a semiconductor chip with solder bumps thereon in contact with corresponding lands of a chip carrier and then heating the chip with the chip carrier to a point at which the solder bumps melt and form joints with the lands of the chip carrier. Often, solder bumps are used which contain a high-lead content solder. Among advantages of the high-lead solder is that it tends to yield to thermal and mechanical stresses within the package. Recently however, industry is trending away from use of high-lead content solder, or rather, towards increased use of lead-free solder. Currently, the future use of lead-containing solder is in question.
Apart from the trend towards lead-free solders, the packaging of microelectronic chips poses significant challenges, particularly the reduction in pitch and size of contacts, high power density, and large area of certain chips such as processor chips.